Analytical Delay Metric for On-chip Rlcg Interconnect for Generalised Input

In this paper we have put forward an analytical model, which could accurately capture the on chip interconnect delay. As we move onto higher frequency range, of the order of GHz, the effects of shunt conductance cannot be ignored, as it provides a measure of the possible leakage. Due to this reason, we have derived our on-chip interconnect delay metric considering distributed RLCG segments, rather than sticking to the conventional RLC and RC. We develop a novel analytical model based on the first few moments of the interconnect transfer function when the input is generalised signal. Delay estimate using our first moment based analytical model is within 3% of SPICE-computed delay, and model based on first two moments is within 2% of SPICE, across a wide range of interconnects parameter values.